The existing IPL only supports booting from 2 QSPI flash chips connected in parallel which is the case on the ZCU102 and ZCU106 EVBs. However, the ZCU104 only has a single flash chip so booting from QSPI flash fails on this board. A new IPL variant is required for the ZCU104 that supports a single flash chip configuration.
The solution is to reconfigure the generic FIFO command templates to match the configuration on the board. The changes have been made in the IPL - qspi.c: qspi_load() and qspi.h, as well as the offsets in the two scripts to flash the images. Below is the summary:
--- IPL ---
In qspi.h (located in ../src/hardware/ipl/boards/xzynq-zcu102/):
- IFS Offset have been changed to 0x02000000
- Max size for BOOT.BIN and IFS has been increased to 32 MB.
- FIFO command templates have been modified to work with one NOR flash chip, i.e. select the correct Chip Select (CS), Data Bus (DB) and Stripe bits in the FIFO commands. You can review the TRM to understand the changes, Chapter 24: Quad-SPI Controllers - Generic Command FIFO:
https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf
In qspi.c (located in ../src/hardware/ipl/boards/xzynq-zcu102/):
- Do not divide down the QSPI offset by 2 when in single chip mode.
The Bootgen utility, which is used in the mkflashimage script to rebuild the BOOT.BIN file, is available via the Xilinx website - https://www.xilinx.com/. For more information about Bootgen, please review the Bootgen User Guide:
NOTE:
This entry has been validated against the SDP version listed above. Use
caution when considering this advice for any other SDP version. For
supported releases, please reach out toQNX Technical Support if you have any questions/concerns.
